i2c-imc-skylake: validate the write path end to end

The driver advertises SMBus byte and word writes but no write to a real
device had been exercised in this cycle. Engine-level evidence existed -- a
write to an unpopulated address returns -ENXIO with the address NACK
reported, so writes are issued rather than suppressed -- but nothing showed
a populated device accepting one.

Driven through the sibling project's CLI, which uses the framing decoded in
its own protocol notes: a 12-write frame to the LED controller at 0x27 on
both channels, latch open, effect id, brightness, three colour bytes, latch
commit. Every write acknowledged, no NACK, no interference reported, and
the device applied the result.

This also settles SMB_DIS_WRT, which is set in the documented SMBCNTL and
is SMM-writable only: it governs the documented interface, not this path.

No SPD was written at any point. The four SPD EEPROMs were verified present
with valid CRCs before and after every experiment in this cycle.

docs/submission/cover-letter.txt

@@ -149,16 +149,16 @@ Validation
     on this system.
   - SMBCNTL on all four iMC channels reads 0xac000000: TSOD polling
     disabled, TSOD_PRESENT empty.
-  - Write transactions reach the bus: a byte write to an unpopulated
-    address returns -ENXIO with the engine reporting the address NACK, so
-    the write path is issued rather than suppressed.  An end-to-end write
-    to a populated device is not part of this validation; the only
-    non-SPD device on the test system is an LED controller whose reads are
-    themselves unreliable, and SPD writes were out of scope.
+  - Writes validated end to end against a populated device: a 12-write
+    frame to an LED controller at 0x27, across both channels, every write
+    acknowledged, no NACK, and the device applied the result.  A byte
+    write to an unpopulated address returns -ENXIO with the engine
+    reporting the address NACK.  No SPD was written at any point, and the
+    four SPD EEPROMs were verified present with valid CRCs before and
+    after.
 
 Still missing: an independent Tested-by, ideally on Skylake-X rather than
-Cascade Lake-X, suspend/resume testing with active I2C clients, and an
-end-to-end write to a populated device.
+Cascade Lake-X, and suspend/resume testing with active I2C clients.
 
 One note on the register interface, since a reader with the datasheet will
 ask.  That document describes an SMBus interface on the iMC channel