Simone
3cd1d6e0a6
The driver reached the PCU function's config space by walking the ACPI MCFG
table and mapping the ECAM page itself. That is one leaf driver deciding
config-space policy, and no other driver in mainline does it, so it was the
single most likely reason for a NAK.
Move that decision where it belongs: the upstream series is now two patches,
a PCI/x86 accessor that forces the memory-mapped path with the core's
locking, and this driver on top of it. Reviewers on each side now get
something they can act on, and get_maintainer.pl selects the PCI and x86
people by itself.
Correctness work in the same pass:
- the completion bits are latched, so a command the engine never accepted
was indistinguishable from a completed one and returned the previous
transaction's data as valid. Require a positive sign that the engine
acted on the command;
- compare the command registers after every transfer against what the
driver left in them and fail with -EAGAIN on a mismatch. The original
iMC driver had this check and it is what makes an unarbitrated system
detectable instead of silently wrong;
- use the i2c core's suspended-adapter mechanism rather than a private
flag and -EHOSTDOWN;
- use devm_mutex_init(), drop the unnecessary pci_enable_device(), and
return -ENODEV rather than -EPERM from the default-off gate, which was
printing a driver-core error on every boot;
- mask GO when restoring a saved command word.
Stop attributing the dropped CF8/CFC write to System Management Mode. The
only evidence was a boot log line naming the access method, which says
nothing about who filters the write. tools/probe-cf8-write.sh is there to
settle it with an MSR_SMI_COUNT measurement.
Add Documentation/i2c/busses/i2c-imc-skylake.rst, which every other PC SMBus
driver has and which was explicitly asked for on the 2020 iMC thread, the
tools/ scripts for the hardware measurements the submission still owes, and
compat/pci-mmcfg-compat.h so the driver still builds out-of-tree against a
kernel without the new accessor while the source stays byte-identical to the
submitted patch.
148 lines
3.6 KiB
C
148 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Out-of-tree compatibility shim - NOT part of the upstream submission.
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*
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* i2c-imc-skylake.c reaches the PCU function's config space with
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* pci_mmcfg_read_config() / pci_mmcfg_write_config(), which are added by
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* patch 1/2 of the series ("PCI: provide config access forced through the
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* ECAM path"). A stock kernel does not have them yet.
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*
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* The Makefile force-includes this header when the target kernel lacks those
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* symbols, so the driver source stays byte-identical to the submitted patch
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* while remaining testable on an unpatched kernel. It reimplements the two
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* accessors the way earlier revisions of the driver did it: locate the ECAM
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* base in the ACPI MCFG table and map the function's config page.
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*
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* Limitations, acceptable for a test shim and for nothing else:
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* - a single device at a time (there is one PCU function per system);
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* - dword accesses only, which is all the driver issues;
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* - no participation in the PCI core's config-space locking. That is
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* precisely the problem patch 1/2 exists to solve.
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*/
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#ifndef IMC_PCI_MMCFG_COMPAT_H
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#define IMC_PCI_MMCFG_COMPAT_H
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#include <linux/acpi.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#define IMC_COMPAT_CFG_SIZE 0x1000UL
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static void __iomem *imc_compat_cfg;
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static resource_size_t imc_compat_phys;
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static u64 imc_compat_mmcfg_base(struct pci_dev *pdev)
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{
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unsigned int seg = pci_domain_nr(pdev->bus);
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unsigned int bus = pdev->bus->number;
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struct acpi_table_header *hdr;
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struct acpi_table_mcfg *mcfg;
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struct acpi_mcfg_allocation *e;
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unsigned long n, i;
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u64 base = 0;
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if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_MCFG, 0, &hdr)))
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return 0;
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mcfg = (struct acpi_table_mcfg *)hdr;
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if (hdr->length < sizeof(*mcfg)) {
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acpi_put_table(hdr);
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return 0;
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}
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e = (struct acpi_mcfg_allocation *)(mcfg + 1);
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n = (hdr->length - sizeof(*mcfg)) / sizeof(*e);
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for (i = 0; i < n; i++) {
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if (e[i].pci_segment == seg &&
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bus >= e[i].start_bus_number &&
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bus <= e[i].end_bus_number) {
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base = e[i].address;
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break;
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}
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}
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acpi_put_table(hdr);
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return base;
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}
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static void imc_compat_unmap(void *data)
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{
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iounmap(imc_compat_cfg);
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imc_compat_cfg = NULL;
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imc_compat_phys = 0;
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}
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static void __iomem *imc_compat_map(struct pci_dev *pdev)
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{
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resource_size_t phys;
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u64 base;
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base = imc_compat_mmcfg_base(pdev);
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if (!base)
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return NULL;
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phys = base +
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((resource_size_t)pdev->bus->number << 20) +
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((resource_size_t)PCI_SLOT(pdev->devfn) << 15) +
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((resource_size_t)PCI_FUNC(pdev->devfn) << 12);
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if (phys < base || phys + IMC_COMPAT_CFG_SIZE < phys)
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return NULL;
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if (imc_compat_cfg && imc_compat_phys == phys)
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return imc_compat_cfg;
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if (imc_compat_cfg)
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return NULL; /* a second device would need a real cache */
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imc_compat_cfg = ioremap_uc(phys, IMC_COMPAT_CFG_SIZE);
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if (!imc_compat_cfg)
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return NULL;
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imc_compat_phys = phys;
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if (devm_add_action_or_reset(&pdev->dev, imc_compat_unmap, NULL))
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return NULL;
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return imc_compat_cfg;
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}
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static inline int pci_mmcfg_read_config(struct pci_dev *dev, int where,
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int size, u32 *val)
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{
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void __iomem *cfg;
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if (size != 4 || (where & 3) || where + size > 0x1000) {
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*val = ~0U;
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return -EINVAL;
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}
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cfg = imc_compat_map(dev);
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if (!cfg) {
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*val = ~0U;
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return -ENXIO;
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}
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*val = readl(cfg + where);
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return 0;
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}
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static inline int pci_mmcfg_write_config(struct pci_dev *dev, int where,
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int size, u32 val)
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{
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void __iomem *cfg;
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if (size != 4 || (where & 3) || where + size > 0x1000)
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return -EINVAL;
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cfg = imc_compat_map(dev);
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if (!cfg)
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return -ENXIO;
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writel(val, cfg + where);
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return 0;
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}
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#endif /* IMC_PCI_MMCFG_COMPAT_H */
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