Simone
2c7675a104
P2 asked whether the ENE at 0x27 has readable state. The answer had been reached twice by elimination, and the last link in that chain was a comment in a third party's patched OpenRGB detector, not a measurement of ours. probe-ene-receive-byte.sh runs the experiment the driver made possible on 2026-07-27, when PNTR_SEL (BIT(18)) gave us a bare Receive Byte: a read with no command byte on the wire cannot return a transform of a register that was never sent. It does, however, return the last command byte the chip received — 12/12 on both channels — so the value is still ours, not the device's. A Receive Byte taken from 0x31 after addressing 0x27 answers 0xff instead of the echo, which places the latch in the device and not in the iMC engine; empty addresses NACK, so the transaction is real. Everything here is read-only: Receive Byte and Read Byte Data at 0x27, SPD reads through ee1004 sysfs, and the four SPD serials compared before and after every run. Two engine behaviours the script has to work around, both measured: the first transaction on a channel answers with a stale value (hence the discarded warm-up read), and a read following a successful one usually NACKs, which one retry always clears — the P1 policy, confirmed. lore-thread-check.py is unrelated to the probe but shares the same motive: lore and patchwork now sit behind an Anubis bot check, so a shell cannot tell "not published" from "not allowed to look". The NNTP mirror can.
41 lines
1.8 KiB
Plaintext
41 lines
1.8 KiB
Plaintext
== P2 Receive Byte probe at 0x27 — 2026-08-10T18:30:45+02:00
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driver: /lib/modules/7.0.0-28-generic/updates/dkms/i2c-imc-skylake.ko.zst
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rounds per channel: 8
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-- SPD baseline
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ch0.dimm0=50E4333A
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ch0.dimm1=1FE43236
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ch1.dimm0=50E434BA
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ch1.dimm1=1EE433B5
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-- ch0 (i2c-1) — does receive_byte echo the last command byte?
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probe_reg read_byte_data receive_byte verdict
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0x33 0x0c 0x33 ECHOES the command byte
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0x55 0x15 0x55 ECHOES the command byte
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0x77 0x1d 0x77 ECHOES the command byte
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0xa5 0x29 0xa5 ECHOES the command byte
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0x0c 0xc1 0x0c ECHOES the command byte
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0x33 0x0c 0x33 ECHOES the command byte
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cross-address: command byte to 0x27, Receive Byte from 0x31
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0x27 reg 0x5a -> 0x16 then 0x31 receive_byte -> 0xff
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0x27 reg 0x3c -> 0x0f then 0x31 receive_byte -> 0xff
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-- ch1 (i2c-2) — does receive_byte echo the last command byte?
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probe_reg read_byte_data receive_byte verdict
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0x33 0x0c 0x33 ECHOES the command byte
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0x55 0x15 0x55 ECHOES the command byte
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0x77 0x1d 0x77 ECHOES the command byte
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0xa5 0x29 0xa5 ECHOES the command byte
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0x0c 0xc3 0x0c ECHOES the command byte
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0x33 0x0c 0x33 ECHOES the command byte
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cross-address: command byte to 0x27, Receive Byte from 0x31
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0x27 reg 0x5a -> 0x16 then 0x31 receive_byte -> 0xff
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0x27 reg 0x3c -> 0x0f then 0x31 receive_byte -> 0xff
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-- SPD after
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ch0.dimm0=50E4333A
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ch0.dimm1=1FE43236
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ch1.dimm0=50E434BA
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ch1.dimm1=1EE433B5
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SPD integrity: OK (4/4 serials unchanged)
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