Simone
7bac49b4f6
All of this came out of a self-review of v3 plus one robot report; none of it changes what the driver supports. The read-back check required the whole command word to come back as written, and the interference check on the driven channel compared against the pre-transfer word. Both implicitly demanded that every undocumented bit of the command register reads as zero, which held on the test system but is not something to assume across steppings. Compare only the bits this driver produces, with the post-write read-back as the baseline for the driven channel; GO clearing remains the single permitted difference. Read the result before the interference check, not after, so the check also covers the window in which the data latch is read. Re-run the TSOD-polling check on resume and keep the adapters suspended if firmware enabled polling across suspend; the probe-time refusal cannot see that, and the S3 observation in the cover letter is exactly this scenario. Stop before writing a saved command word back if the config read that fetched it had already failed. Rename the register accessors: the command register is CMD and the data latch DATA. v3 called the command register DATA and the data latch CTRL, which read backwards. Cast ~COMMAND_OUR_BITS to u32 in the interference check. BIT() and GENMASK() are unsigned long, so the complement was computed in 64 bits and truncated on assignment; the truncated value was already correct, this only silences a clang W=1 -Wconstant-conversion warning. Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ The Kconfig help and the .rst now say that PCI ID 8086:2085 also matches Skylake-SP / Cascade Lake-SP servers, where a BMC is far more likely to own the engine, and the .rst states plainly that jc42 itself has not been run here, only the transactions it needs.
30 lines
1.3 KiB
Plaintext
30 lines
1.3 KiB
Plaintext
config I2C_IMC_SKYLAKE
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tristate "Intel Skylake-X iMC SMBus adapter"
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depends on PCI && (X86_64 || COMPILE_TEST)
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select I2C_SMBUS
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help
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Say Y here if you want kernel support for the integrated memory
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controller (iMC) SMBus engine found in Intel Skylake-X / Cascade
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Lake-X processors (socket LGA 2066, platform X299, PCU function
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8086:2085).
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Two I2C adapters are registered, one per hardware SMBus channel,
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allowing access to DDR4 DIMM SPD EEPROMs (0x50-0x57) and thermal
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sensors from userspace via standard i2c-tools and lm-sensors.
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SPD EEPROMs are instantiated automatically from DMI, so decode-dimms
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works without any manual step.
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Firmware, SMM, a BMC or CLTT may drive the same engine and no
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generic arbitration mechanism is known. The driver therefore
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refuses to bind unless the allow_unsafe_access module parameter
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is enabled. See Documentation/i2c/busses/i2c-imc-skylake.rst.
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If unsure, say N. This driver is aimed at Intel X299 desktop /
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HEDT systems with a Skylake-X or Cascade Lake-X CPU. The same PCI
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ID appears on Skylake-SP / Cascade Lake-SP servers, where a BMC is
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far more likely to be using the engine already; the driver applies
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the same checks there, but saying N is even more advisable.
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This driver can also be built as a module. If so, the module
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will be called i2c-imc-skylake.
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