Simone
88a8b7eb27
v2 said firmware filters CF8/CFC config writes to this function and that
the registers are reachable only through ECAM. That was never tested; the
only evidence was the boot line "PCI: Using configuration type 1", which
names the accessor and says nothing about a write failing.
Measured on the board, driver unloaded:
# setpci -s 16:1e.5 9c.L=20085002 # read SPD 0x50 register 0x02
# setpci -s 16:1e.5 9c.L
20005002 # GO consumed by the engine
# setpci -s 16:1e.5 a8.L
0000500c # READ_DONE, no error
# setpci -s 16:1e.5 b4.L
0000000c # SPD byte 2, DDR4 type code
The command executes and returns correct data through the ordinary
accessors, and MSR_SMI_COUNT does not move across it. So the driver now
uses pci_read_config_dword() and pci_write_config_dword(), the submission
is a single patch again, and nothing in it touches the PCI core. The
cover letter retracts the claim explicitly rather than dropping it
quietly, because v2 was posted with it.
Correctness work in the same pass:
- the completion bits are latched, so a command word that never reaches
the register is indistinguishable from a completed transfer and the
caller gets the previous transaction's data. Read the command word
back and require it to be the one just written; the engine only ever
clears GO, which the measurement above shows directly;
- compare the command registers after every transfer against what the
driver left in them and fail with -EAGAIN on a mismatch. The original
iMC driver had this check and it is what makes an unarbitrated system
detectable instead of silently wrong;
- use the i2c core's suspended-adapter mechanism rather than a private
flag and -EHOSTDOWN;
- use devm_mutex_init(), drop the unnecessary pci_enable_device(), and
return -ENODEV rather than -EPERM from the default-off gate, which was
printing a driver-core error on every boot;
- mask GO when restoring a saved command word.
An earlier version of the latched-DONE check required the GO bit to be
seen set or the status word to change. That was wrong: repeated transfers
with the same outcome leave STATUS bit for bit identical, and GO is
consumed faster than a config read-back can observe it. It produced false
positives on 3 of 15 smoke-test items before being replaced.
Add Documentation/i2c/busses/i2c-imc-skylake.rst, which every other PC
SMBus driver has and which was asked for on the 2020 iMC thread, and the
tools/ scripts for the hardware measurements: probe-cf8-write.sh and
probe-cf8-transaction.sh produced the result above, dump-pcu-config.sh is
the search for a TSOD polling control, watch-engine.sh is the firmware
activity measurement.
Smoke test on the X299 system with the current module: 15 checks, 0
failures, dmesg clean.
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24 lines
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config I2C_IMC_SKYLAKE
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tristate "Intel Skylake-X iMC SMBus adapter"
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depends on PCI && (X86_64 || COMPILE_TEST)
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help
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Say Y here if you want kernel support for the integrated memory
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controller (iMC) SMBus engine found in Intel Skylake-X / Cascade
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Lake-X processors (socket LGA 2066, platform X299, PCU function
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8086:2085).
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Two I2C adapters are registered, one per hardware SMBus channel,
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allowing access to DDR4 DIMM SPD EEPROMs (0x50-0x57) and thermal
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sensors from userspace via standard i2c-tools and lm-sensors.
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Firmware, SMM, a BMC or CLTT may drive the same engine and no
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generic arbitration mechanism is known. The driver therefore
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refuses to bind unless the allow_unsafe_access module parameter
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is enabled. See Documentation/i2c/busses/i2c-imc-skylake.rst.
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If unsure, say N. This driver is only useful on Intel X299 desktop
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/ HEDT systems with the Skylake-X or Cascade Lake-X CPU.
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This driver can also be built as a module. If so, the module
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will be called i2c-imc-skylake.
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