Simone
6bf5879a9f
Add support for I2C_SMBUS_QUICK and I2C_SMBUS_BYTE transfers to maintain compatibility with older userspace tools (e.g., legacy i2cdetect versions). - I2C_SMBUS_QUICK: Emulated as read-byte from offset 0, allowing device probing without sending data. - I2C_SMBUS_BYTE: For reads, the command byte becomes the register offset; for writes, the command byte is the value written to offset 0. This preserves the LKML v3 corrections (channel index, FRAME decomposition, timeout documentation, ECAM overflow checks) while adding backward compatibility for tools that expect QUICK/BYTE support. Note: This functionality is only in the compat branch and will not be submitted upstream, as the hardware requires a register offset for every transaction.
581 lines
18 KiB
C
581 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel Skylake-X iMC SMBus I2C adapter.
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*
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* The integrated memory controller (iMC) on Intel Skylake-X / Cascade Lake-X
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* processors exposes an SMBus engine used to reach the SPD EEPROMs and thermal
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* sensors on DDR4 DIMMs. The engine is driven through the PCI configuration
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* space of the Sky Lake-E PCU function (0000:16:1e.5, 8086:2085). This driver
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* presents that engine as two standard Linux I2C adapters - one per hardware
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* SMBus channel - so that i2c-tools and lm-sensors can use it without bespoke
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* sysfs hacks.
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*
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* Why ECAM MMIO instead of the usual CF8/CFC config accessors:
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* On this platform System Management Mode (SMM) traps and mangles port-based
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* (CF8/CFC) writes to the first 256 config bytes of this function, so the SMBus
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* command never completes. The boot log reports "PCI: Using configuration
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* type 1 (probe)" confirming the default path is port-based; the MMCONFIG
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* (ECAM) window is not trapped. Windows' NTIOLib reaches the registers via
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* ECAM, which is how we confirmed the register layout on hardware. We map the
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* ECAM page of the target function and drive the registers by MMIO, exactly as
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* the firmware does.
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*
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* ECAM phys(off) = mmcfg_base + (bus<<20) + (dev<<15) + (fn<<12) + off
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* mmcfg_base is read from the ACPI MCFG table at probe time (not hardcoded).
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*
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* Per-channel register triple within the config page:
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* ch0 ch1
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* CTRL (data) 0xB4 0xB8 write: data byte in bits[23:16]; read: low byte
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* DATA (cmd) 0x9C 0xA0 FRAME | (cmd << 8) | reg ; bit19 = GO
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* STATUS 0xA8 0xAC busy while bit0 set; done when clear,
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* bit1 (0x02) set on completion = device NACKed
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* SMBus command byte (DATA bits[15:8]) = (rw << 7) | addr7: the 7-bit slave
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* address with bit7 = direction (1 write / 0 read). The register/offset goes
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* in DATA[7:0]. So 0x50 reads SPD EEPROM 0x50. This was decoded and
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* confirmed on hardware.
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*
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* The two channels are independent SMBus buses (DIMMs 1,2 on ch0; DIMMs 3,4 on
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* ch1), hence two i2c_adapter instances exposed as separate /dev/i2c-* nodes.
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* Each channel carries the DIMM SPD EEPROMs (0x50-0x57) and thermal sensors -
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* all reachable by 7-bit address.
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*
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* Bus arbitration / concurrency with firmware:
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* The engine could in principle also be driven by SMM or by the iMC's own
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* closed-loop thermal throttling (CLTT) TSOD polling. On the X299 HEDT
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* platform there is no BMC and CLTT firmware polling is not active, so the
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* quiesce handshake required on server parts (Sandy Bridge-EP, Broadwell-E)
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* is not needed here. On the tested hardware the engine is idle at probe
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* and no firmware-initiated transaction has ever been observed between
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* driver transactions. The global mutex still serialises the two channels
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* against each other, as they share a single engine.
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*/
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#include <linux/acpi.h>
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#include <linux/bits.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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/* expected PCI id of the Sky Lake-E PCU SMBus function */
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#define PCU_DEVICE 0x2085
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#define PCU_ID ((PCU_DEVICE << 16) | PCI_VENDOR_ID_INTEL)
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#define CFG_SIZE 0x1000UL
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/* function-global config registers (offsets within the config page) */
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#define CFG_VENDOR_DEV 0x00 /* cfg[0]: vendor/device id, for ECAM sanity check */
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#define CFG_IMC_BUS 0xCC /* cfg[0xCC] bits[15:8]: iMC SMBus bus number */
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/* per-channel register offsets within the config page */
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#define CH0_CTRL 0xB4
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#define CH0_DATA 0x9C
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#define CH0_STAT 0xA8
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#define CH1_CTRL 0xB8
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#define CH1_DATA 0xA0
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#define CH1_STAT 0xAC
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/*
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* Command word written to the DATA register:
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* bits[31:16] = FRAME (engine config + GO bit19), constant
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* bits[15:8] = SMBus command byte = (rw << 7) | addr7
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* rw bit (0x80): 1 = write, 0 = read
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* addr7 : 7-bit SMBus slave address
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* bits[7:0] = register/offset within the addressed device
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* For a write the data byte is latched into CTRL[23:16] beforehand. This
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* encoding was confirmed on hardware: command 0x50 reads SPD EEPROM 0x50
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* (DDR4 signature).
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*/
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#define ENGINE_ENABLE BIT(29) /* engine enable bit */
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#define GO_BIT BIT(19) /* start transaction */
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#define FRAME (ENGINE_ENABLE | GO_BIT)
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#define RW_WRITE 0x80 /* OR into the command byte for a write */
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#define WORD_BIT BIT(17) /* 16-bit word transfer (vs 8-bit byte) */
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#define STAT_BUSY BIT(0) /* low bit set while transaction in flight */
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#define STAT_NACK BIT(1) /* set on completion if the device NACKed */
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struct imc_chan {
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u32 ctrl, data, stat;
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int idx; /* channel index 0 or 1 */
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};
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static const struct imc_chan imc_chans[2] = {
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{ CH0_CTRL, CH0_DATA, CH0_STAT, 0 },
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{ CH1_CTRL, CH1_DATA, CH1_STAT, 1 },
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};
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/* one driver state object, shared by both per-channel adapters */
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struct imc_smbus {
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struct device *dev; /* &pdev->dev, for dev_*() logging */
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void __iomem *cfg; /* ioremapped ECAM page of the function */
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struct mutex lock; /* serialises all SMBus transactions */
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/* needed: both channels share same ECAM mapping */
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struct i2c_adapter adap[2]; /* one per hardware channel */
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};
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/*
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* ECAM base discovery from ACPI MCFG. acpi_table_parse() is not exported to
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* modules, so map the MCFG table with acpi_get_table() (exported) and walk the
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* allocation entries by hand. Uses pdev's PCI segment and bus number so no
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* module parameter override is needed. CONFIG_ACPI is guaranteed by Kconfig.
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*/
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static u64 imc_detect_mmcfg_base(struct pci_dev *pdev)
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{
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unsigned int seg = pci_domain_nr(pdev->bus);
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unsigned int bus = pdev->bus->number;
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struct acpi_table_header *hdr;
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struct acpi_table_mcfg *mcfg;
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struct acpi_mcfg_allocation *e;
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unsigned long n, i;
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u64 base = 0;
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if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_MCFG, 0, &hdr)))
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return 0;
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mcfg = (struct acpi_table_mcfg *)hdr;
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if (hdr->length < sizeof(*mcfg)) {
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acpi_put_table(hdr);
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return 0;
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}
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e = (struct acpi_mcfg_allocation *)(mcfg + 1);
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n = (hdr->length - sizeof(*mcfg)) / sizeof(*e);
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for (i = 0; i < n; i++) {
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if (e[i].pci_segment == seg &&
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bus >= e[i].start_bus_number &&
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bus <= e[i].end_bus_number) {
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base = e[i].address;
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break;
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}
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}
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acpi_put_table(hdr);
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return base;
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}
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/*
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* Wait until GO clears (transaction issued), then until the busy bit drops.
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* Returns 0 on completion, -ETIMEDOUT if the engine never went idle. On
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* success *status (if non-NULL) gets the final status word. Process context
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* only - it sleeps between polls.
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*
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* On the test system (Skylake-X, 4 DDR4 DIMMs) transactions complete in a few
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* milliseconds; the 200ms (GO clear) and 50ms (BUSY clear) timeouts leave a
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* generous margin for SMM interference and SMBus clock stretching.
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*/
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static int imc_wait(struct imc_smbus *s, const struct imc_chan *c, u32 *status)
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{
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u32 val;
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int ret;
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ret = readl_poll_timeout(s->cfg + c->data, val, !(val & GO_BIT), 10, 200000);
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if (ret)
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return ret;
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ret = readl_poll_timeout(s->cfg + c->stat, val, !(val & STAT_BUSY), 10, 50000);
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if (ret)
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return ret;
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if (status)
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*status = val;
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return 0;
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}
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/*
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* Poll the busy bit clear only (no GO check). The firmware polls STATUS after
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* the CTRL (data-latch) write too, before issuing the DATA/GO word.
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* Timeout: 50ms, same rationale as in imc_wait().
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*
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* Note: devm_ioremap_uc() returns an uncached (UC) mapping, which enforces
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* strong ordering. writel() includes a full mb() barrier, ensuring the write
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* is visible to hardware before polling begins.
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*/
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static int imc_wait_status(struct imc_smbus *s, const struct imc_chan *c)
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{
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u32 val;
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int ret;
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ret = readl_poll_timeout(s->cfg + c->stat, val, !(val & STAT_BUSY), 10, 50000);
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if (ret) {
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dev_dbg(s->dev, "pre-command poll timed out, engine still busy\n");
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return ret;
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}
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return 0;
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}
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/* translate a completed transaction's status into an errno (0 = ACK) */
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static int imc_check_status(struct imc_smbus *s, u32 status, u8 addr, u8 reg)
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{
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if (status & STAT_NACK) {
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/* no device at this address, or it refused the access */
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dev_dbg(s->dev, "addr 0x%02x reg 0x%02x NACK (stat 0x%08x)\n",
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addr, reg, status);
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return -ENXIO;
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}
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return 0;
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}
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/* SMBus write-byte to addr: latch the data byte, then issue the command. */
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static int imc_write_byte(struct imc_smbus *s, const struct imc_chan *c,
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u8 addr, u8 reg, u8 val)
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{
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u32 status = 0;
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int ret;
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writel((u32)val << 16, s->cfg + c->ctrl);
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ret = imc_wait_status(s, c);
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if (ret)
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return ret;
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writel(FRAME | ((u32)(addr | RW_WRITE) << 8) | reg, s->cfg + c->data);
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ret = imc_wait(s, c, &status);
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if (ret) {
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dev_warn_ratelimited(s->dev,
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"write addr 0x%02x reg 0x%02x timed out\n",
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addr, reg);
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return ret;
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}
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ret = imc_check_status(s, status, addr, reg);
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if (ret)
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return ret;
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return 0;
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}
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/* SMBus read-byte from addr: issue the command, return the low data byte. */
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static int imc_read_byte(struct imc_smbus *s, const struct imc_chan *c,
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u8 addr, u8 reg, u8 *val)
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{
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u32 status = 0;
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int ret;
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ret = imc_wait_status(s, c);
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if (ret)
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return ret;
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writel(FRAME | ((u32)addr << 8) | reg, s->cfg + c->data);
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ret = imc_wait(s, c, &status);
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if (ret) {
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dev_warn_ratelimited(s->dev,
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"read addr 0x%02x reg 0x%02x timed out\n",
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addr, reg);
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return ret;
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}
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ret = imc_check_status(s, status, addr, reg);
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if (ret)
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return ret;
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*val = readl(s->cfg + c->ctrl) & 0xFF;
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return 0;
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}
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/*
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* SMBus write-word to addr: latch the 16-bit value into CTRL[31:16], then
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* issue the command with WORD_BIT set. The value is byte-swapped between host
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* order and the engine's CTRL byte layout (swab16) so that data->word follows
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* the standard SMBus convention (low data byte first). The read path applies
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* the inverse swap.
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*
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* Validated on hardware: a WORD read returns the same byte order as two
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* consecutive BYTE_DATA reads (word low byte == register R, high byte == R+1),
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* confirmed against DDR4 SPD bytes. This is exactly the convention jc42 relies
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* on via i2c_smbus_read_word_swapped(), so no double swap occurs.
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*/
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static int imc_write_word(struct imc_smbus *s, const struct imc_chan *c,
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u8 addr, u8 reg, u16 val)
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{
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u32 status = 0;
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int ret;
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/* host order -> engine CTRL byte order (see function comment) */
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writel((u32)swab16(val) << 16, s->cfg + c->ctrl);
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ret = imc_wait_status(s, c);
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if (ret)
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return ret;
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writel(FRAME | WORD_BIT | ((u32)(addr | RW_WRITE) << 8) | reg,
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s->cfg + c->data);
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ret = imc_wait(s, c, &status);
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if (ret) {
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dev_warn_ratelimited(s->dev,
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"write word addr 0x%02x reg 0x%02x timed out\n",
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addr, reg);
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return ret;
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}
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return imc_check_status(s, status, addr, reg);
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}
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/*
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* SMBus read-word from addr: issue the command with WORD_BIT set, return the
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* 16-bit value from CTRL[15:0] byte-swapped back to host order (inverse of the
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* write path). See imc_write_word() for the byte-order convention.
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*/
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static int imc_read_word(struct imc_smbus *s, const struct imc_chan *c,
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u8 addr, u8 reg, u16 *val)
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{
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u32 status = 0, raw;
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int ret;
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ret = imc_wait_status(s, c);
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if (ret)
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return ret;
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writel(FRAME | WORD_BIT | ((u32)addr << 8) | reg, s->cfg + c->data);
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ret = imc_wait(s, c, &status);
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if (ret) {
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dev_warn_ratelimited(s->dev,
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"read word addr 0x%02x reg 0x%02x timed out\n",
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addr, reg);
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return ret;
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}
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ret = imc_check_status(s, status, addr, reg);
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if (ret)
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return ret;
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raw = readl(s->cfg + c->ctrl) & 0xFFFF;
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*val = swab16(raw);
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return 0;
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}
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/*
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* Standard SMBus transfer callback. The per-channel imc_chan is stashed in the
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* adapter's algo_data. The command word carries the 7-bit address, so
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* SPD EEPROMs (0x50-0x57) are reachable on each channel. BYTE_DATA and
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* WORD_DATA are supported; larger transfers would need the engine's block
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* primitives, which are not used by the devices on this bus.
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*/
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static s32 imc_smbus_xfer(struct i2c_adapter *adap, u16 addr,
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unsigned short flags, char read_write, u8 command,
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int size, union i2c_smbus_data *data)
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{
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struct imc_smbus *s = i2c_get_adapdata(adap);
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const struct imc_chan *c = adap->algo_data;
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u8 reg, val = 0;
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int ret;
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if (addr > 0x7f)
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return -EINVAL;
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/*
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* Emulate I2C_SMBUS_QUICK as a read-byte from offset 0.
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* This allows i2cdetect to probe devices without sending data.
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*/
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if (size == I2C_SMBUS_QUICK) {
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mutex_lock(&s->lock);
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ret = imc_read_byte(s, c, addr, 0, &val);
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mutex_unlock(&s->lock);
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return ret;
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}
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if (size != I2C_SMBUS_BYTE && size != I2C_SMBUS_BYTE_DATA &&
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size != I2C_SMBUS_WORD_DATA)
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return -EOPNOTSUPP;
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/*
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* Every transaction on this engine carries a register/offset byte. For
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* BYTE_DATA the SMBus "command" is that register; for plain BYTE there
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* is no register phase, so offset 0 is used (read = receive-byte;
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* write = the command byte is the value written to offset 0).
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*/
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switch (size) {
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case I2C_SMBUS_BYTE:
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reg = (read_write == I2C_SMBUS_WRITE) ? 0 : command;
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break;
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case I2C_SMBUS_BYTE_DATA:
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case I2C_SMBUS_WORD_DATA:
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reg = command;
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break;
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default:
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return -EOPNOTSUPP;
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}
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mutex_lock(&s->lock);
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if (read_write == I2C_SMBUS_WRITE) {
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if (size == I2C_SMBUS_WORD_DATA) {
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dev_dbg(s->dev, "ch%d W addr=%02x reg=%02x val=%04x\n",
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c->idx, addr, reg, data->word);
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ret = imc_write_word(s, c, addr, reg, data->word);
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} else {
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val = (size == I2C_SMBUS_BYTE) ? command : data->byte;
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dev_dbg(s->dev, "ch%d W addr=%02x reg=%02x val=%02x\n",
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c->idx, addr, reg, val);
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ret = imc_write_byte(s, c, addr, reg, val);
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}
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} else {
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if (size == I2C_SMBUS_WORD_DATA) {
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u16 wval = 0;
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ret = imc_read_word(s, c, addr, reg, &wval);
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if (!ret)
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data->word = wval;
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dev_dbg(s->dev, "ch%d R addr=%02x reg=%02x -> %04x (ret %d)\n",
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c->idx, addr, reg, wval, ret);
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} else {
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ret = imc_read_byte(s, c, addr, reg, &val);
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if (!ret)
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data->byte = val;
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dev_dbg(s->dev, "ch%d R addr=%02x reg=%02x -> %02x (ret %d)\n",
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c->idx, addr, reg, val, ret);
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}
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}
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mutex_unlock(&s->lock);
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return ret;
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}
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static u32 imc_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA;
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}
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static const struct i2c_algorithm imc_algo = {
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.smbus_xfer = imc_smbus_xfer,
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.functionality = imc_func,
|
|
};
|
|
|
|
static void imc_mutex_destroy(void *data)
|
|
{
|
|
struct mutex *lock = data;
|
|
|
|
mutex_destroy(lock);
|
|
}
|
|
|
|
static int imc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
resource_size_t phys;
|
|
struct imc_smbus *s;
|
|
u8 imc_bus_hw;
|
|
u64 base;
|
|
u32 cfg0, cc;
|
|
int ret, i;
|
|
|
|
s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
|
|
if (!s)
|
|
return -ENOMEM;
|
|
|
|
ret = pcim_enable_device(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "cannot enable PCI device: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
s->dev = &pdev->dev;
|
|
mutex_init(&s->lock);
|
|
ret = devm_add_action_or_reset(&pdev->dev, imc_mutex_destroy, &s->lock);
|
|
if (ret)
|
|
return ret;
|
|
|
|
base = imc_detect_mmcfg_base(pdev);
|
|
if (!base) {
|
|
dev_err(&pdev->dev, "cannot resolve MMCONFIG base\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
phys = base +
|
|
((resource_size_t)pdev->bus->number << 20) +
|
|
((resource_size_t)PCI_SLOT(pdev->devfn) << 15) +
|
|
((resource_size_t)PCI_FUNC(pdev->devfn) << 12);
|
|
|
|
if (phys < base || phys + CFG_SIZE < phys) {
|
|
dev_err(&pdev->dev, "ECAM address overflow\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Deliberately no request_mem_region(): the MMCONFIG window is already
|
|
* claimed as a firmware/PCI resource, so a reservation would fail with
|
|
* -EBUSY. The pci_driver binding keeps the function alive; the registers
|
|
* we drive are side-band controls the kernel does not otherwise touch.
|
|
*/
|
|
s->cfg = devm_ioremap_uc(&pdev->dev, phys, CFG_SIZE);
|
|
if (!s->cfg) {
|
|
dev_err(&pdev->dev, "ioremap(%pa) failed\n", &phys);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
cfg0 = readl(s->cfg + CFG_VENDOR_DEV);
|
|
if (cfg0 != PCU_ID) {
|
|
dev_err(&pdev->dev, "wrong device at ECAM %pa (cfg[0]=0x%08x)\n",
|
|
&phys, cfg0);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* Cross-check the iMC bus number against the configuration register
|
|
* value: cfg[0xCC] bits[15:8] = the iMC SMBus bus number as seen by
|
|
* the PCU. On all known Skylake-X / Cascade Lake-X boards this matches
|
|
* the probed bus number.
|
|
* A mismatch means the ECAM walk landed on the wrong slot — warn but
|
|
* continue; the binding is already locked to 8086:2085.
|
|
*/
|
|
cc = readl(s->cfg + CFG_IMC_BUS);
|
|
imc_bus_hw = (cc >> 8) & 0xFF;
|
|
|
|
if (imc_bus_hw && imc_bus_hw != (u8)pdev->bus->number)
|
|
dev_warn(&pdev->dev,
|
|
"cfg[0xCC] reports iMC bus 0x%02x but probed bus=0x%02x\n",
|
|
imc_bus_hw, (u8)pdev->bus->number);
|
|
else
|
|
dev_dbg(&pdev->dev,
|
|
"cfg[0xCC]=0x%08x iMC bus 0x%02x confirmed\n",
|
|
cc, imc_bus_hw);
|
|
|
|
dev_dbg(&pdev->dev, "ECAM mapped at %pa\n", &phys);
|
|
|
|
/*
|
|
* Lifetime safety: the I2C core guarantees that smbus_xfer callbacks
|
|
* are not invoked after i2c_del_adapter() returns. Since we use
|
|
* devm_i2c_add_adapter(), the adapter is automatically removed on
|
|
* driver detach, and no concurrent xfer can be in flight at that point.
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(s->adap); i++) {
|
|
struct i2c_adapter *a = &s->adap[i];
|
|
int n;
|
|
|
|
a->owner = THIS_MODULE;
|
|
a->algo = &imc_algo;
|
|
a->algo_data = (void *)&imc_chans[i];
|
|
a->dev.parent = &pdev->dev;
|
|
i2c_set_adapdata(a, s);
|
|
n = snprintf(a->name, sizeof(a->name),
|
|
"iMC SMBus Skylake-X channel %d", i);
|
|
if (n >= sizeof(a->name))
|
|
dev_warn(&pdev->dev, "adapter name truncated\n");
|
|
|
|
ret = devm_i2c_add_adapter(&pdev->dev, a);
|
|
if (ret) {
|
|
dev_err(&pdev->dev,
|
|
"i2c_add_adapter ch%d failed: %d\n", i, ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
dev_dbg(&pdev->dev, "registered 2 SMBus channels\n");
|
|
return 0;
|
|
}
|
|
|
|
static const struct pci_device_id imc_pci_ids[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCU_DEVICE) },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, imc_pci_ids);
|
|
|
|
/*
|
|
* All resources (ioremap, i2c adapters, mutex) are devm-managed and are
|
|
* released automatically after probe returns or during device unbinding, so
|
|
* no .remove callback is needed. The register state is deliberately left
|
|
* as-is on unbind: the engine carries no driver-private latched state that
|
|
* needs teardown, and the SMBus controls we drive are side-band registers the
|
|
* rest of the kernel does not touch.
|
|
*/
|
|
static struct pci_driver imc_driver = {
|
|
.name = "i2c-imc-skylake",
|
|
.id_table = imc_pci_ids,
|
|
.probe = imc_pci_probe,
|
|
};
|
|
module_pci_driver(imc_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Simone Chifari");
|
|
MODULE_DESCRIPTION("Intel Skylake-X iMC SMBus I2C adapter (ECAM MMIO)");
|