Simone
fee48bba23
Apply senior-review feedback to the driver, validated on hardware
(Skylake-X / X299). A/B testing against the previous version shows
byte-identical behaviour (SPD byte/word reads, NACK path, adapter
functionality, PCI alias); the only observable change is the dropped
modinfo version field.
- Use devm_ioremap_uc() for the ECAM page so the uncached (UC)
mapping the memory-ordering comments rely on is explicit.
- Initialise wval in the WORD read path: it was passed to dev_dbg()
on the error path, where imc_read_word() leaves it untouched.
- Drop MODULE_VERSION() (discouraged for in-tree drivers).
- Iterate over ARRAY_SIZE(s->adap) instead of the literal 2.
- Name the config-space offsets (CFG_VENDOR_DEV, CFG_IMC_BUS).
- Restrict Kconfig to X86_64 (Skylake-X is 64-bit only).
- Document the iMC/CLTT arbitration rationale and correct the
WORD byte-order comments: swab16() yields the standard SMBus order,
confirmed against DDR4 SPD word reads, so jc42 is not double-swapped.
Signed-off-by: Simone Chifari <simone.chifari@gmail.com>
19 lines
860 B
Plaintext
19 lines
860 B
Plaintext
config I2C_IMC_SKYLAKE
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tristate "Intel Skylake-X iMC SMBus adapter"
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depends on PCI && ACPI && X86_64
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help
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Say Y here if you want kernel support for the integrated memory
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controller (iMC) SMBus engine found in Intel Skylake-X / Cascade
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Lake-X processors (socket LGA 2066, platform X299, PCU function
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8086:2085).
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The engine is exposed through the PCI configuration space of the
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PCU function and is driven via ECAM MMIO (not CF8/CFC port I/O,
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which is trapped by System Management Mode on this platform).
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Two I2C adapters are registered, one per hardware SMBus channel,
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allowing access to DDR4 DIMM SPD EEPROMs (0x50-0x57) and thermal
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sensors from userspace via standard i2c-tools and lm-sensors.
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If unsure, say N. This driver is only useful on Intel X299 desktop
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/ HEDT systems with the Skylake-X or Cascade Lake-X CPU.
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