chore: initial commit (extracted from Launchers monorepo)
Plugin: ns7zip v2.0.0 Architectures: x86-ansi, x86-unicode, amd64-unicode License: LGPL-2.1-or-later
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/* Sort.c -- Sort functions
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: Igor Pavlov : Public domain */
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#include "Precomp.h"
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#include "Sort.h"
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#include "CpuArch.h"
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#if ( (defined(__GNUC__) && (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))) \
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|| (defined(__clang__) && Z7_has_builtin(__builtin_prefetch)) \
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)
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// the code with prefetch is slow for small arrays on x86.
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// So we disable prefetch for x86.
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#ifndef MY_CPU_X86
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// #pragma message("Z7_PREFETCH : __builtin_prefetch")
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#define Z7_PREFETCH(a) __builtin_prefetch((a))
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#endif
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#elif defined(_WIN32) // || defined(_MSC_VER) && (_MSC_VER >= 1200)
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#include "7zWindows.h"
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// NOTE: CLANG/GCC/MSVC can define different values for _MM_HINT_T0 / PF_TEMPORAL_LEVEL_1.
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// For example, clang-cl can generate "prefetcht2" instruction for
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// PreFetchCacheLine(PF_TEMPORAL_LEVEL_1) call.
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// But we want to generate "prefetcht0" instruction.
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// So for CLANG/GCC we must use __builtin_prefetch() in code branch above
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// instead of PreFetchCacheLine() / _mm_prefetch().
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// New msvc-x86 compiler generates "prefetcht0" instruction for PreFetchCacheLine() call.
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// But old x86 cpus don't support "prefetcht0".
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// So we will use PreFetchCacheLine(), only if we are sure that
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// generated instruction is supported by all cpus of that isa.
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#if defined(MY_CPU_AMD64) \
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|| defined(MY_CPU_ARM64) \
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|| defined(MY_CPU_IA64)
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// we need to use additional braces for (a) in PreFetchCacheLine call, because
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// PreFetchCacheLine macro doesn't use braces:
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// #define PreFetchCacheLine(l, a) _mm_prefetch((CHAR CONST *) a, l)
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// #pragma message("Z7_PREFETCH : PreFetchCacheLine")
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#define Z7_PREFETCH(a) PreFetchCacheLine(PF_TEMPORAL_LEVEL_1, (a))
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#endif
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#endif // _WIN32
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#define PREFETCH_NO(p,k,s,size)
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#ifndef Z7_PREFETCH
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#define SORT_PREFETCH(p,k,s,size)
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#else
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// #define PREFETCH_LEVEL 2 // use it if cache line is 32-bytes
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#define PREFETCH_LEVEL 3 // it is fast for most cases (64-bytes cache line prefetch)
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// #define PREFETCH_LEVEL 4 // it can be faster for big array (128-bytes prefetch)
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#if PREFETCH_LEVEL == 0
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#define SORT_PREFETCH(p,k,s,size)
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#else // PREFETCH_LEVEL != 0
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/*
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if defined(USE_PREFETCH_FOR_ALIGNED_ARRAY)
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we prefetch one value per cache line.
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Use it if array is aligned for cache line size (64 bytes)
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or if array is small (less than L1 cache size).
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if !defined(USE_PREFETCH_FOR_ALIGNED_ARRAY)
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we perfetch all cache lines that can be required.
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it can be faster for big unaligned arrays.
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*/
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#define USE_PREFETCH_FOR_ALIGNED_ARRAY
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// s == k * 2
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#if 0 && PREFETCH_LEVEL <= 3 && defined(MY_CPU_X86_OR_AMD64)
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// x86 supports (lea r1*8+offset)
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#define PREFETCH_OFFSET(k,s) ((s) << PREFETCH_LEVEL)
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#else
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#define PREFETCH_OFFSET(k,s) ((k) << (PREFETCH_LEVEL + 1))
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#endif
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#if 1 && PREFETCH_LEVEL <= 3 && defined(USE_PREFETCH_FOR_ALIGNED_ARRAY)
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#define PREFETCH_ADD_OFFSET 0
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#else
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// last offset that can be reqiured in PREFETCH_LEVEL step:
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#define PREFETCH_RANGE ((2 << PREFETCH_LEVEL) - 1)
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#define PREFETCH_ADD_OFFSET PREFETCH_RANGE / 2
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#endif
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#if PREFETCH_LEVEL <= 3
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#ifdef USE_PREFETCH_FOR_ALIGNED_ARRAY
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#define SORT_PREFETCH(p,k,s,size) \
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{ const size_t s2 = PREFETCH_OFFSET(k,s) + PREFETCH_ADD_OFFSET; \
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if (s2 <= size) { \
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Z7_PREFETCH((p + s2)); \
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}}
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#else /* for unaligned array */
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#define SORT_PREFETCH(p,k,s,size) \
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{ const size_t s2 = PREFETCH_OFFSET(k,s) + PREFETCH_RANGE; \
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if (s2 <= size) { \
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Z7_PREFETCH((p + s2 - PREFETCH_RANGE)); \
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Z7_PREFETCH((p + s2)); \
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}}
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#endif
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#else // PREFETCH_LEVEL > 3
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#ifdef USE_PREFETCH_FOR_ALIGNED_ARRAY
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#define SORT_PREFETCH(p,k,s,size) \
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{ const size_t s2 = PREFETCH_OFFSET(k,s) + PREFETCH_RANGE - 16 / 2; \
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if (s2 <= size) { \
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Z7_PREFETCH((p + s2 - 16)); \
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Z7_PREFETCH((p + s2)); \
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}}
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#else /* for unaligned array */
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#define SORT_PREFETCH(p,k,s,size) \
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{ const size_t s2 = PREFETCH_OFFSET(k,s) + PREFETCH_RANGE; \
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if (s2 <= size) { \
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Z7_PREFETCH((p + s2 - PREFETCH_RANGE)); \
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Z7_PREFETCH((p + s2 - PREFETCH_RANGE / 2)); \
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Z7_PREFETCH((p + s2)); \
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}}
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#endif
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#endif // PREFETCH_LEVEL > 3
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#endif // PREFETCH_LEVEL != 0
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#endif // Z7_PREFETCH
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#if defined(MY_CPU_ARM64) \
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/* || defined(MY_CPU_AMD64) */ \
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/* || defined(MY_CPU_ARM) && !defined(_MSC_VER) */
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// we want to use cmov, if cmov is very fast:
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// - this cmov version is slower for clang-x64.
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// - this cmov version is faster for gcc-arm64 for some fast arm64 cpus.
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#define Z7_FAST_CMOV_SUPPORTED
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#endif
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#ifdef Z7_FAST_CMOV_SUPPORTED
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// we want to use cmov here, if cmov is fast: new arm64 cpus.
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// we want the compiler to use conditional move for this branch
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#define GET_MAX_VAL(n0, n1, max_val_slow) if (n0 < n1) n0 = n1;
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#else
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// use this branch, if cpu doesn't support fast conditional move.
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// it uses slow array access reading:
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#define GET_MAX_VAL(n0, n1, max_val_slow) n0 = max_val_slow;
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#endif
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#define HeapSortDown(p, k, size, temp, macro_prefetch) \
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{ \
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for (;;) { \
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UInt32 n0, n1; \
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size_t s = k * 2; \
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if (s >= size) { \
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if (s == size) { \
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n0 = p[s]; \
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p[k] = n0; \
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if (temp < n0) k = s; \
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} \
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break; \
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} \
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n0 = p[k * 2]; \
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n1 = p[k * 2 + 1]; \
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s += n0 < n1; \
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GET_MAX_VAL(n0, n1, p[s]) \
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if (temp >= n0) break; \
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macro_prefetch(p, k, s, size) \
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p[k] = n0; \
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k = s; \
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} \
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p[k] = temp; \
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}
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/*
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stage-1 : O(n) :
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we generate intermediate partially sorted binary tree:
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p[0] : it's additional item for better alignment of tree structure in memory.
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p[1]
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p[2] p[3]
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p[4] p[5] p[6] p[7]
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...
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p[x] >= p[x * 2]
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p[x] >= p[x * 2 + 1]
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stage-2 : O(n)*log2(N):
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we move largest item p[0] from head of tree to the end of array
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and insert last item to sorted binary tree.
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*/
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// (p) must be aligned for cache line size (64-bytes) for best performance
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void Z7_FASTCALL HeapSort(UInt32 *p, size_t size)
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{
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if (size < 2)
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return;
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if (size == 2)
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{
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const UInt32 a0 = p[0];
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const UInt32 a1 = p[1];
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const unsigned k = a1 < a0;
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p[k] = a0;
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p[k ^ 1] = a1;
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return;
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}
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{
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// stage-1 : O(n)
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// we transform array to partially sorted binary tree.
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size_t i = --size / 2;
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// (size) now is the index of the last item in tree,
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// if (i)
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{
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do
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{
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const UInt32 temp = p[i];
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size_t k = i;
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HeapSortDown(p, k, size, temp, PREFETCH_NO)
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}
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while (--i);
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}
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{
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const UInt32 temp = p[0];
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const UInt32 a1 = p[1];
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if (temp < a1)
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{
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size_t k = 1;
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p[0] = a1;
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HeapSortDown(p, k, size, temp, PREFETCH_NO)
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}
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}
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}
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if (size < 3)
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{
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// size == 2
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const UInt32 a0 = p[0];
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p[0] = p[2];
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p[2] = a0;
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return;
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}
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if (size != 3)
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{
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// stage-2 : O(size) * log2(size):
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// we move largest item p[0] from head to the end of array,
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// and insert last item to sorted binary tree.
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do
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{
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const UInt32 temp = p[size];
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size_t k = p[2] < p[3] ? 3 : 2;
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p[size--] = p[0];
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p[0] = p[1];
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p[1] = p[k];
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HeapSortDown(p, k, size, temp, SORT_PREFETCH) // PREFETCH_NO
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}
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while (size != 3);
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}
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{
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const UInt32 a2 = p[2];
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const UInt32 a3 = p[3];
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const size_t k = a2 < a3;
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p[2] = p[1];
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p[3] = p[0];
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p[k] = a3;
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p[k ^ 1] = a2;
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}
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}
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