Simone
c04e0ec5a8
The engine encodes an address-only transaction in command word bit 18, which is what SMBus Receive Byte and Send Byte need and what was missing for ee1004 to bind. The bit is not documented for the PCU function. It was located by structure rather than by sweeping: SMBCMD on the iMC channel function (datasheet ref. 614073 section 3.1.8) places PNTR_SEL immediately above WORD_ACCESS, and word access here is bit 17. Bit 17 had itself been unknown until it turned out to be word access, and an earlier sweep of this register covered bits 31:20 only, so 18 was untried rather than already ruled out. Validated against the device rather than against the register. An EEPROM auto-increments its pointer after a read, so priming the pointer and repeating the read with the bit set has a predicted answer: the next byte, not the one named. Eight consecutive reads returned SPD bytes 0x01 through 0x08 in order, matching an ordinary dump. Send Byte was confirmed on the DDR4 page-select addresses, which hold a latch and store no data, so the page state is itself the readout. Result: ee1004 binds on all four SPD addresses and decode-dimms decodes all four modules with both CRCs valid on each. The part number comes off page 1, so the page select runs end to end. The four module serial numbers are unchanged from the baseline recorded before this series. SMBus Quick stays unimplemented. Beyond having no obvious encoding, a write into the 0x30-0x37 range is how an EE1004 SPD is write-protected, permanently on many modules, so an adapter on the memory bus should not advertise a probe that writes. i2cdetect scans in read mode. Also fix test-smoke.sh resolving the module through modinfo, which silently tested the installed DKMS build instead of the one just compiled. It now prefers the local .ko and prints which it loaded. Smoke suite: 19 passed, 0 failed. checkpatch --strict 0/0/0, in-tree W=1 and Sparse clean.
136 lines
5.6 KiB
Markdown
136 lines
5.6 KiB
Markdown
# Hardware measurements still owed to the submission
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Three scripts, meant to be run by hand on an X299 (or Cascade Lake-X) system
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with the PCU function `8086:2085`. None of them is run by CI and none is run by
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`make test`.
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Output of all three belongs in the cover letter or in a reply on the list, as
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raw numbers. Do not paraphrase them.
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| Script | Answers | Writes to hardware |
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| --- | --- | --- |
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| `watch-engine.sh` | Is firmware using the engine on this system? | no |
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| `dump-pcu-config.sh` | Which PCU registers move on their own? Is there a TSOD polling control? | no |
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| `probe-cf8-write.sh` | Is the CF8/CFC write really dropped, and does it raise an SMI? | **yes**, requires `--i-understand` |
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## 1. `watch-engine.sh` — foreign activity (read-only)
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Samples the six per-channel registers and reports every change that this
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system's Linux side did not cause. Run it with the driver **unloaded**, so that
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anything observed is firmware.
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```bash
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sudo ./tools/watch-engine.sh --seconds 3600
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```
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What the cover letter needs: a run of at least one hour, ideally across a
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suspend/resume cycle, with the observed change count. A non-zero count on a
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system means the driver must not be loaded there, and is itself a result worth
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reporting.
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## 2. `dump-pcu-config.sh` — register survey (read-only)
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Dumps the function's 4 KB config space twice and diffs them, then prints the
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neighbourhood of the offsets that matter.
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```bash
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sudo ./tools/dump-pcu-config.sh --settle 10
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```
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This is the search for the open item F2: the Broadwell-E iMC driver stops the
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PCU's TSOD polling for the duration of a transfer by writing 0 to `TSODCNTL`
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at offset `0xe0` of its PCU function, waiting 10 ms for in-flight transactions
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to drain, and restoring the value afterwards. No equivalent register has been
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identified on `8086:2085`. A field that changes on its own with a fixed cadence
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is the first candidate.
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## 3. `probe-cf8-write.sh` — the dropped write (WRITES TO HARDWARE)
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This is the only script that writes. It changes the register/offset field of a
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command register while the GO bit is clear, which does not start an SMBus
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transaction, then reads it back and reports whether the write stuck. It also
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reads `MSR_SMI_COUNT` (0x34) on every CPU before and after.
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```bash
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sudo ./tools/probe-cf8-write.sh --i-understand
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```
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Two results matter:
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* the value does **not** read back → the claim "CF8/CFC writes to this function
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do not take effect" is confirmed on the tested board;
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* the SMI delta is **0** → the behaviour is not System Management Mode, and the
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driver's comments and the cover letter must not say it is.
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Requirements: `msr-tools` (`rdmsr`), `pciutils` (`setpci`, `lspci`), and the
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`msr` module (`modprobe msr`).
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## 4. `probe-cf8-transaction.sh` — does CF8/CFC start a transfer? (WRITES TO HARDWARE)
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Follow-up to §3. `probe-cf8-write.sh` shows whether the register accepts a
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value; this shows whether the engine acts on it, by setting the GO bit for a
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read of an unpopulated address and watching STATUS.
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```bash
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sudo ./tools/probe-cf8-transaction.sh --i-understand
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```
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It does start one. That result retired the plan to reach these registers
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through ECAM with a PCI-core change, and the driver uses the ordinary config
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accessors.
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## 5. `probe-imc-documented.sh` — the interface Intel documents (WRITES TO HARDWARE)
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Issues a read through `SMB_STAT`/`SMBCMD`/`SMBCNTL` on the iMC channel
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functions (`8086:2040`), the interface the datasheet describes, rather than the
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PCU registers this driver uses.
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```bash
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sudo ./tools/probe-imc-documented.sh --i-understand
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```
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On the development board it reports `RDO=1, SBE=0, RDATA=0x00` identically for
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a populated 0x50, a populated 0x52 and an absent 0x57: it completes but cannot
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tell a populated slot from an empty one, so it is not reaching this bus.
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## 6. `probe-pntr-sel.sh` — find the address-only bit (read-only on the bus)
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Finds the command-word bit that suppresses the register byte, which is what
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SMBus Receive Byte and Send Byte need.
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```bash
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sudo ./tools/probe-pntr-sel.sh --i-understand --channel 1
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```
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Not a blind sweep. An EEPROM auto-increments its pointer after a read, so
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priming the pointer with an ordinary read and then repeating it with the
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candidate bit set has a predicted answer: the *next* byte, not the one named.
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The script checks that prediction at two different offsets and then walks eight
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consecutive reads, which an ordinary dump must reproduce exactly.
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The answer on this engine is bit 18, matching the position of `PNTR_SEL`
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relative to `WORD_ACCESS` in the documented `SMBCMD` layout. Reads only, and
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never to the page-select addresses, so the DDR4 page latch does not move.
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## 7. `probe-send-byte.sh` — the write half (WRITES TO HARDWARE)
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Confirms the same bit produces a Send Byte, against the page-select addresses
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`0x36`/`0x37`. Those hold a latch and store no data, so the only thing a write
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there can do is choose which half of the SPD is visible — and that choice is
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itself the readout, since byte 0x00 is the JEDEC `0x23` on page 0 and something
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else on page 1. Nothing is written to `0x50`-`0x57`.
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```bash
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sudo ./tools/probe-send-byte.sh --i-understand --channel 0 --restore
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```
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`--restore` is the safe first run: it targets a channel already stuck on page 1
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and selects page 0, so a working Send Byte repairs that channel and a broken one
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leaves it exactly as found. There is no outcome worse than the starting state.
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`--flip` does the full round trip on a healthy channel, after `--restore` has
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shown the encoding works.
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A channel found on page 1 is not a fault of this driver: `ee1004`, and
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OpenRGB's `DDR4DirectAccessor::set_page()`, both select a page and leave it
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selected.
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